Not easily satisfied with what's printed in architecture briefs or reviewer's guides, PC Games Hardware has been nagging Nvidia with questions about their new Fermi architecture and the just launched Geforce GTX 480 and 470.

What's the official number of transistors? 3 billion was announced, 3.2 made it into the rumor mill and "more than 3 billion" is given in the papers. Well, it turns out, 3 billion is the number of little transistors that's included in each and every GF100-GPU.

Clock Domains: Nvidia states a 700/607 MHz engine clock for 480 and 470 respectively. But what parts of the engine run at this speed? Does this also include ROPs and L2-Cache or do those run in another clock domain? The answer we got was, that the engine clock refers to all key units. Except for the shader core itself, which runs at the so called hot clock (1400 MHz for GTX 480 and 1215 MHz for GTX 470). Also not included is the memory interface, but unfortunately Nvidia did not make it clear, if that's only the controllers or also the attached units like L2-Cache or Octo-ROPs.

Regarding Load/Store units: As we've learnt, there are 16 of them per shader multiprocessor, thus yielding a convenient number of 256 for the whole chip an 240 for a GTX 480. Operating on atomic values, that'd be a perfect fit to double for fetching textures. But as Nvidia told us, that's not the case. Because LD/ST is separate from the texture fetch path. The Load/Store units use a different path, through the L1, then L2, then Framebuffer. Texture units first look in texture cache (there's 12k each), then L2 cache, then FB memory.


Geometry: 700*4 = 648*8? No way! At the presentation of the Geforce part of the architecture at CES, Nvidia stated that Fermi (no Geforce-name was given then!) would have 8x the geometry throughput of GT200. How did they arrive at that number? Wasn't GT200 1 tri/clock, whereas Fermi is 4 tris/clock (both theoretical maxs)? Well, Nvidias Fermi's theoretical peak for tessellated geometry is 4 drawn triangles per clk. They said it's hard to compare exactly to GT200 since GT200 does not support tessellation. Cnsidering GT200's lower clock and lower peak triangle rate (which is only 0.5 drawn triangles per clk and 1 tri per clk is valid only for culled triangles), and serial geometry processing pipeline, 8x was a reasonable estimate of performance difference between the architectures. They added, that 4 drawn triangles per clock would be the theoretical peak and that the actually achieved tessellated triangle rates would depend on many factors including tessellation program, nature of the geometry etc, and that they are not expecting to hit the peak rate. Instead, other sources pointed at 3.2 triangles per clock as reasonable number for real-life peaks.